echo Project Status
Project File: echo.xise Parser Errors: No Errors
Module Name: echo Implementation State: Programming File Generated
Target Device: xc7a100t-1csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 0 126,800 0%  
Number of Slice LUTs 0 63,400 0%  
Number of occupied Slices 0 15,850 0%  
Number of LUT Flip Flop pairs used 0      
Number of bonded IOBs 16 210 7%  
    Number of LOCed IOBs 16 16 100%  
Number of RAMB36E1/FIFO36E1s 0 135 0%  
Number of RAMB18E1/FIFO18E1s 0 270 0%  
Number of BUFG/BUFGCTRLs 0 32 0%  
Number of IDELAYE2/IDELAYE2_FINEDELAYs 0 300 0%  
Number of ILOGICE2/ILOGICE3/ISERDESE2s 0 300 0%  
Number of ODELAYE2/ODELAYE2_FINEDELAYs 0      
Number of OLOGICE2/OLOGICE3/OSERDESE2s 0 300 0%  
Number of PHASER_IN/PHASER_IN_PHYs 0 24 0%  
Number of PHASER_OUT/PHASER_OUT_PHYs 0 24 0%  
Number of BSCANs 0 4 0%  
Number of BUFHCEs 0 96 0%  
Number of BUFRs 0 24 0%  
Number of CAPTUREs 0 1 0%  
Number of DNA_PORTs 0 1 0%  
Number of DSP48E1s 0 240 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of IBUFDS_GTE2s 0 4 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 6 0%  
Number of IN_FIFOs 0 24 0%  
Number of MMCME2_ADVs 0 6 0%  
Number of OUT_FIFOs 0 24 0%  
Number of PCIE_2_1s 0 1 0%  
Number of PHASER_REFs 0 6 0%  
Number of PHY_CONTROLs 0 6 0%  
Number of PLLE2_ADVs 0 6 0%  
Number of STARTUPs 0 1 0%  
Number of XADCs 0 1 0%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent周一 8月 19 21:06:23 2019000
Translation ReportCurrent周一 8月 19 21:06:30 2019000
Map ReportCurrent周一 8月 19 21:06:46 2019005 Infos (0 new)
Place and Route ReportCurrent周一 8月 19 21:07:02 2019002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrent周一 8月 19 21:07:13 2019004 Infos (0 new)
Bitgen ReportCurrent周一 8月 19 21:07:36 2019001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent周一 8月 19 21:07:37 2019
WebTalk Log FileCurrent周一 8月 19 21:07:41 2019

Date Generated: 08/19/2019 - 21:12:24