Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (ISE) - P.20131013 Target Family: Artix7
OS Platform: NT64 Target Device: xc7a100t
Project ID (random number) 24baec093edb444bb40c26c3ad1a4f08.0F287E0B59B2424A8CC153EB9C655FEC.2 Target Package: csg324
Registration ID 211351018_0_0_323 Target Speed: -1
Date Generated 2019-08-19T21:21:40 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-7700HQ CPU @ 2.80GHz CPU Speed 2808 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-7700HQ CPU @ 2.80GHz CPU Speed 2808 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=1
  • 27-bit comparator greater=1
Counters=1
  • 27-bit up counter=1
MiscellaneousStatistics
  • AGG_BONDED_IO=17
  • AGG_IO=17
  • AGG_LOCED_IO=17
  • AGG_SLICE=21
  • NUM_BONDED_IOB33=17
  • NUM_BSFULL=27
  • NUM_BSLUTONLY=34
  • NUM_BSUSED=61
  • NUM_BUFG=1
  • NUM_LOCED_IOB33=17
  • NUM_LOGIC_O5ANDO6=6
  • NUM_LOGIC_O5ONLY=25
  • NUM_LOGIC_O6ONLY=29
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=25
  • NUM_SLICEL=21
  • NUM_SLICE_CARRY4=7
  • NUM_SLICE_CONTROLSET=2
  • NUM_SLICE_CYINIT=93
  • NUM_SLICE_F7MUX=1
  • NUM_SLICE_FF=27
  • NUM_SLICE_UNUSEDCTRL=13
  • NUM_UNUSABLE_FF_BELS=5
NetStatistics
  • NumNets_Active=98
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BENTQUAD=47
  • NumNodesOfType_Active_BOUNCEACROSS=15
  • NumNodesOfType_Active_BOUNCEIN=8
  • NumNodesOfType_Active_BUFGROUT=1
  • NumNodesOfType_Active_BUFINP2OUT=1
  • NumNodesOfType_Active_CLKPIN=9
  • NumNodesOfType_Active_DOUBLE=74
  • NumNodesOfType_Active_GENERIC=10
  • NumNodesOfType_Active_GLOBAL=15
  • NumNodesOfType_Active_HQUAD=8
  • NumNodesOfType_Active_INPUT=9
  • NumNodesOfType_Active_IOBIN2OUT=17
  • NumNodesOfType_Active_IOBOUTPUT=17
  • NumNodesOfType_Active_LUTINPUT=127
  • NumNodesOfType_Active_OUTBOUND=81
  • NumNodesOfType_Active_OUTPUT=72
  • NumNodesOfType_Active_PADINPUT=8
  • NumNodesOfType_Active_PADOUTPUT=9
  • NumNodesOfType_Active_PINBOUNCE=24
  • NumNodesOfType_Active_PINFEED=146
  • NumNodesOfType_Active_SINGLE=114
  • NumNodesOfType_Active_VLONG12=1
  • NumNodesOfType_Active_VQUAD=52
  • NumNodesOfType_Vcc_HVCCGNDOUT=12
  • NumNodesOfType_Vcc_LUTINPUT=31
  • NumNodesOfType_Vcc_PINFEED=31
SiteStatistics
  • BUFG-BUFGCTRL=1
  • IOB33-IOB33M=8
  • IOB33-IOB33S=8
  • SLICEL-SLICEM=7
SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=7
  • HARD0=1
  • IOB33=17
  • IOB33_INBUF_EN=9
  • IOB33_OUTBUF=8
  • LUT5=31
  • LUT6=61
  • PAD=17
  • REG_INIT=27
  • SELMUX2_1=1
  • SLICEL=21
 
Configuration Data
IOB33_INBUF_EN
  • IBUF_LOW_PWR=[TRUE:9]
IOB_INBUF_EN
  • IBUF_LOW_PWR=[TRUE:9]
REG_INIT
  • CK=[CK:27] [CK_INV:0]
  • FFINIT=[INIT0:27]
  • FFSR=[SRLOW:27]
  • LATCH_OR_FF=[FF:27]
  • SYNC_ATTR=[ASYNC:22] [SYNC:5]
SELMUX2_1
  • 0=[0:1] [0_INV:0]
SLICEL
  • CLK=[CLK:8] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
BUFG_BUFG
  • I0=1
  • O=1
CARRY4
  • CIN=6
  • CO3=6
  • CYINIT=1
  • DI0=7
  • DI1=7
  • DI2=6
  • DI3=6
  • O0=7
  • O1=7
  • O2=7
  • O3=6
  • S0=7
  • S1=7
  • S2=7
  • S3=6
HARD0
  • 0=1
IOB
  • I=9
  • O=8
  • PAD=17
IOB33
  • I=9
  • O=8
  • PAD=17
IOB33_INBUF_EN
  • OUT=9
  • PAD=9
IOB33_OUTBUF
  • IN=8
  • OUT=8
IOB_INBUF_EN
  • INTERMDISABLE=9
  • OUT=9
  • PAD=9
IOB_OUTBUF
  • IN=8
  • OUT=8
LUT5
  • A2=4
  • A3=5
  • A4=1
  • A5=1
  • O5=31
LUT6
  • A1=4
  • A2=6
  • A3=6
  • A4=17
  • A5=56
  • A6=60
  • O6=61
PAD
  • PAD=17
REG_INIT
  • CK=27
  • D=27
  • Q=27
  • SR=5
SELMUX2_1
  • 0=1
  • 1=1
  • OUT=1
  • S0=1
SLICEL
  • A=4
  • A1=1
  • A2=4
  • A3=4
  • A4=6
  • A5=16
  • A6=17
  • AMUX=8
  • AQ=7
  • B=1
  • B3=1
  • B4=2
  • B5=12
  • B6=13
  • BMUX=7
  • BQ=6
  • C=1
  • C1=1
  • C2=1
  • C3=1
  • C4=3
  • C5=13
  • C6=14
  • CIN=6
  • CLK=8
  • CMUX=6
  • COUT=6
  • CQ=8
  • CX=1
  • D=4
  • D1=2
  • D2=5
  • D3=5
  • D4=6
  • D5=15
  • D6=16
  • DMUX=7
  • DQ=6
  • SR=2
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc7a100t-csg324-1 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc7a100t-csg324-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc7a100t-csg324-1 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc7a100t-csg324-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 4 4 0 0 0 0 0
map 4 4 0 0 0 0 0
ngdbuild 4 4 0 0 0 0 0
par 4 4 0 0 0 0 0
trce 4 4 0 0 0 0 0
xst 3 3 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_VHDLSourceAnalysisStandard=VHDL-200X
PROP_intProjectCreationTimestamp=2019-08-19T21:12:49 PROP_intWbtProjectID=0F287E0B59B2424A8CC153EB9C655FEC
PROP_intWbtProjectIteration=2 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_AutoTop=true PROP_DevFamily=Artix7
PROP_DevDevice=xc7a100t PROP_DevFamilyPMName=artix7
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-1 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=22 NGDBUILD_NUM_FDR=5 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=8 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=26 NGDBUILD_NUM_LUT2=31
NGDBUILD_NUM_LUT3=2 NGDBUILD_NUM_LUT5=2 NGDBUILD_NUM_LUT6=4 NGDBUILD_NUM_MUXCY=26
NGDBUILD_NUM_MUXF7=1 NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=27
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=22 NGDBUILD_NUM_FDR=5 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=8 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=26
NGDBUILD_NUM_LUT2=31 NGDBUILD_NUM_LUT3=2 NGDBUILD_NUM_LUT5=2 NGDBUILD_NUM_LUT6=4
NGDBUILD_NUM_MUXCY=26 NGDBUILD_NUM_MUXF7=1 NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=27
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc7a100t-1-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=32 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5