wave Project Status (08/19/2019 - 21:21:45)
Project File: wave.xise Parser Errors: No Errors
Module Name: wave Implementation State: Programming File Generated
Target Device: xc7a100t-1csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
1 Warning (1 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 27 126,800 1%  
    Number used as Flip Flops 27      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 61 63,400 1%  
    Number used as logic 60 63,400 1%  
        Number using O6 output only 29      
        Number using O5 output only 25      
        Number using O5 and O6 6      
        Number used as ROM 0      
    Number used as Memory 0 19,000 0%  
    Number used exclusively as route-thrus 1      
        Number with same-slice register load 0      
        Number with same-slice carry load 1      
        Number with other load 0      
Number of occupied Slices 21 15,850 1%  
Number of LUT Flip Flop pairs used 61      
    Number with an unused Flip Flop 34 61 55%  
    Number with an unused LUT 0 61 0%  
    Number of fully used LUT-FF pairs 27 61 44%  
    Number of unique control sets 2      
    Number of slice register sites lost
        to control set restrictions
5 126,800 1%  
Number of bonded IOBs 17 210 8%  
    Number of LOCed IOBs 17 17 100%  
Number of RAMB36E1/FIFO36E1s 0 135 0%  
Number of RAMB18E1/FIFO18E1s 0 270 0%  
Number of BUFG/BUFGCTRLs 1 32 3%  
    Number used as BUFGs 1      
    Number used as BUFGCTRLs 0      
Number of IDELAYE2/IDELAYE2_FINEDELAYs 0 300 0%  
Number of ILOGICE2/ILOGICE3/ISERDESE2s 0 300 0%  
Number of ODELAYE2/ODELAYE2_FINEDELAYs 0      
Number of OLOGICE2/OLOGICE3/OSERDESE2s 0 300 0%  
Number of PHASER_IN/PHASER_IN_PHYs 0 24 0%  
Number of PHASER_OUT/PHASER_OUT_PHYs 0 24 0%  
Number of BSCANs 0 4 0%  
Number of BUFHCEs 0 96 0%  
Number of BUFRs 0 24 0%  
Number of CAPTUREs 0 1 0%  
Number of DNA_PORTs 0 1 0%  
Number of DSP48E1s 0 240 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of IBUFDS_GTE2s 0 4 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 6 0%  
Number of IN_FIFOs 0 24 0%  
Number of MMCME2_ADVs 0 6 0%  
Number of OUT_FIFOs 0 24 0%  
Number of PCIE_2_1s 0 1 0%  
Number of PHASER_REFs 0 6 0%  
Number of PHY_CONTROLs 0 6 0%  
Number of PLLE2_ADVs 0 6 0%  
Number of STARTUPs 0 1 0%  
Number of XADCs 0 1 0%  
Average Fanout of Non-Clock Nets 1.85      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent周一 8月 19 21:17:29 201901 Warning (1 new)0
Translation ReportCurrent周一 8月 19 21:20:29 2019000
Map ReportCurrent周一 8月 19 21:20:49 2019005 Infos (0 new)
Place and Route ReportCurrent周一 8月 19 21:21:05 2019003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrent周一 8月 19 21:21:16 2019004 Infos (0 new)
Bitgen ReportCurrent周一 8月 19 21:21:39 2019001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent周一 8月 19 21:21:40 2019
WebTalk Log FileCurrent周一 8月 19 21:21:44 2019

Date Generated: 08/19/2019 - 21:21:45