Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (ISE) - P.20131013 Target Family: Artix7
OS Platform: NT64 Target Device: xc7a100t
Project ID (random number) 24baec093edb444bb40c26c3ad1a4f08.14A3D1BB3B1F4C6C8F96D71801381D99.2 Target Package: csg324
Registration ID 211351018_0_0_323 Target Speed: -1
Date Generated 2019-08-19T21:07:37 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-7700HQ CPU @ 2.80GHz CPU Speed 2808 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-7700HQ CPU @ 2.80GHz CPU Speed 2808 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=16
  • AGG_IO=16
  • AGG_LOCED_IO=16
  • NUM_BONDED_IOB33=16
  • NUM_LOCED_IOB33=16
NetStatistics
  • NumNets_Active=24
  • NumNodesOfType_Active_BENTQUAD=9
  • NumNodesOfType_Active_BOUNCEACROSS=1
  • NumNodesOfType_Active_BOUNCEIN=1
  • NumNodesOfType_Active_DOUBLE=6
  • NumNodesOfType_Active_GENERIC=8
  • NumNodesOfType_Active_IOBIN2OUT=16
  • NumNodesOfType_Active_IOBOUTPUT=16
  • NumNodesOfType_Active_OUTBOUND=16
  • NumNodesOfType_Active_PADINPUT=8
  • NumNodesOfType_Active_PADOUTPUT=8
  • NumNodesOfType_Active_PINBOUNCE=2
  • NumNodesOfType_Active_PINFEED=8
  • NumNodesOfType_Active_SINGLE=6
  • NumNodesOfType_Active_VLONG=2
  • NumNodesOfType_Active_VQUAD=15
SiteStatistics
  • IOB33-IOB33M=7
  • IOB33-IOB33S=8
SiteSummary
  • IOB33=16
  • IOB33_INBUF_EN=8
  • IOB33_OUTBUF=8
  • PAD=16
 
Configuration Data
IOB33_INBUF_EN
  • IBUF_LOW_PWR=[TRUE:8]
IOB_INBUF_EN
  • IBUF_LOW_PWR=[TRUE:8]
 
Pin Data
HARD0
  • 0=8
IOB
  • I=8
  • O=8
  • PAD=16
IOB33
  • I=8
  • O=8
  • PAD=16
IOB33_INBUF_EN
  • OUT=8
  • PAD=8
IOB33_OUTBUF
  • IN=8
  • OUT=8
IOB_INBUF_EN
  • INTERMDISABLE=8
  • OUT=8
  • PAD=8
IOB_OUTBUF
  • IN=8
  • OUT=8
PAD
  • PAD=16
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc7a100t-csg324-1 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc7a100t-csg324-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc7a100t-csg324-1 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc7a100t-csg324-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 2 2 0 0 0 0 0
map 2 2 0 0 0 0 0
ngdbuild 2 2 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 2 2 0 0 0 0 0
xst 2 2 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_VHDLSourceAnalysisStandard=VHDL-200X
PROP_intProjectCreationTimestamp=2019-08-19T21:02:47 PROP_intWbtProjectID=14A3D1BB3B1F4C6C8F96D71801381D99
PROP_intWbtProjectIteration=2 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_AutoTop=true PROP_DevFamily=Artix7
PROP_DevDevice=xc7a100t PROP_DevFamilyPMName=artix7
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-1 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=8 NGDBUILD_NUM_OBUF=8
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=8 NGDBUILD_NUM_OBUF=8
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc7a100t-1-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=32 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5